Projeto Eficiente de Arquiteturas de Hardware Dedicadas para o Módulo das Transformadas na Codificação de Sinais Visuais: Estudo de Caso no Codificador AV1

Abstract

Nowadays, there is a growing demand for content that manipulates and displays visual signals, such as images, videos, and Light Fields. However, due to the large volume of data present in these types of visual signals, data compression is essential to enable their storage and/or transmission. One of the key steps in all current visual data compression systems is the transforms stage, which is responsible for enabling greater compression of the energy present in the samples and the separation of all frequency components presented in images and videos. In current encoders, the transforms stage has brought various innovations, allowing better data exploration and greater efficiency in compressing videos. To deal with all these innovations and challenges for the transforms stage, implementation in dedicated hardware is a technological alternative that provides the necessary performance to achieve the processing required for high resolutions, such as UHD, while also ensuring acceptable levels of energy consumption. In this context, this Thesis focuses on the development of dedicated architectures for the transforms module in visual signal encoding, using the AV1 encoder as a case study to demonstrate the results. Thus, various archi tectural solutions for the transforms stage were investigated and explored, bringing novel contributions to the state-of-the-art and demonstrating a flow for the design of hardware architectures for the transforms module that can also be used for other visual signal encoders. The development of the work involved the elaboration of a script aimed at automatically generating the transforms kernels and accelerating the architectural design. More than 27 different versions of architectures for the transforms module were explored, covering the development of three versions for different 1D transforms and nine versions for the transposition buffers. The designed architectures were synthesized in ASIC using the Genus Compiler tool and the 40nm and 60nm libraries from TSMC. The synthesis results demonstrate that the complete 2D-SD-B16-RED-OLB and 2D-SD-SRAM-RED architectures, after all optimization stages and using Multi-VTh libraries of the 40nm technology, presented area results of 778.88kgates and 621.92kgates, with power dissipation of 69.11mW and 71.05mW, respectively, when operating at a frequency of 104.98MHz to achieve processing of UHD 4K videos at 60 frames per second. At the moment that this Thesis is being written, no other work proposing a dedicated hardware solution for the 2D transforms of the AV1 encoder was found in the literature.