Dedicated Hardware Architectures for the Affine Motion Estimation of Versatile Video Coding Video Standard for Real-Time UHD Videos

Abstract

The demand for streaming digital videos over the internet has significantly increased in recent years. This substantial rise in video data traffic requires efficient compression techniques for storage and transmission. Moreover, these compression techniques must preserve image quality while addressing energy consumption and real-time pro cessing constraints. In this context, the Versatile Video Coding (VVC) compression standard, also known as H.266, is the state-of-the-art video compression standard re leased in July 2020 by the Joint Video Experts Team (JVET). VVC introduced several new tools to aid video compression compared to its pre decessor, the H.265/HEVC standard. This results in significant gains in compression efficiency (the ratio of bit rate reduction to the encoded video quality), allowing for more efficient transmission or storage of digital videos. One of the new tools added in VVC is Affine prediction, which is used to characterize non-translational motion. This new tool has the highest computational cost in the entire inter-frame prediction stage of the VVC encoder. However, Affine prediction can provide gains of up to 2.18% in compression efficiency (BD-Rate) in exchange for a 5.26% increase in encoding time. Affine prediction supports two versions, using four or six parameters, where two or three motion vectors are used, respectively. These vectors are inherited from the reference block to be encoded and are used for reconstructing the block. This work was designed and synthesized using ASIC hardware architectures for the Affine motion estimation in the VVC standard, focusing on low energy consumption. The architectural design emphasizes the capability to process real-time UHD 4K videos (3840 × 2160), aiming for its application in mobile devices. Three architectures are presented: One for Affine motion compensation with an area utilization of 189k Gates and 121mW power dissipation. Another for the architecture that calculates the Affine ∆MV with 245k Gates and 31mW of power dissipation. Also, an initial version of the gradient-based coefficient generator is presented with 6,900k Gates and 4.8W power dissipation.