Balanced secure triple track logic: uma nova topologia segura contra ataques DPA e DEMA utilizando técnica de uniformização de consumo

Abstract

The cryptography is responsible to guarantee the data secrecy. Nowadays, the algorithms are public domain and the data security relies in cryptographic secret keys. Although, techniques have been developed aiming acquire these keys granting access to the secret information. Differential Power Analysis (DPA) is an attack technique that exploit the relation between the power consumption and the processed data. Aiming neutralize this threat, many countermeasures researches have been developed by scientific community. In this context, this work introduces an DPA countermeasure strategy applicate in VLSI technology. This strategy composes two consolidates topologies, the Secure Triple Track Logic (STTL) and the Pre-Charge Static Logic (PCSL). The STTL and PCSL are countermeasures in gate-level topologies that focus in consumption homogenization. STTL adds a validation track that signalizes when the inputs and outputs are stable and may be computed. It eliminates the undesirable switches generate by the instability in the intermediate signals of the circuit. The PCSL adds redundant transistors in its composition that aims reach the gate symmetry. Therefore, minimizing the internal capacitive discrepancies. Although, this work verified that STTL and PCSL have problems that implies in data-dependency. The STTL has an unbalanced transistors arrangement while the PCSL has the instability that STTL proposes to solve. This work introduces the Balanced Secure Triple Track Logic (BSTTL) that composes the STTL and PCSL strategies and benefits. To verify the BSTTL benefits, are used two community metrics that quantifies the devices DPA vulnerabilities and electric simulations. Additionally, these metrics are used in the basics gates And, Nand, Or and Nor and circuits DES SBox1 and AES Serpent Sbox as cases studies. The BSTTL reaches 3.9x safer than the previous topologies with frequency of operation of 990KHz in the Serpent and 350KHz in SBox of DES. These benefits are obtained through cost in circuit area and consumption.