Avaliação de um método iterativo na etapa de mapeamento tecnológico

Abstract

Currently, the manufacturing process of integrated circuits allow us to build electronic devices with a very large scale of integration. However, every new advances on new technologies to overcome physical limits brings new challenges for designers. Electronic Design Automation (EDA) tools have been used to help on the circuit design and on the evolution of the physical and logic synthesis. This work is focused on the logic synthesis step, regarding technology mapping methods. Considering the covering step in technology mapping, there are several problems related to data structure and minimization function. Thus, the complexity involved in this step can be a Np-hard problem. This way, there are many heuristics for to solve this covering problem. Among the heuristics of literature the iterative methods has been highlighted. So, this work proposed an evaluation of the iterative methodology based in Simulated Annealing. The Simulated Annealing (SA) heuristic is commonly used on physical synthesis. However, we could not find any work related to that and technology mapping. Therefore, we propose an evaluation of a new iterative approach for technology mapping that uses the SA technique. It was developed over the FlexMap framework, and several experiments have been made in order to evaluate the impact of some parameters used in the SA heuristic on the quality of the mapped circuit. The experiments were made for two technologies, FPGAs and Quantum Cellular Automata (QCA), aiming the minimization of the number of logical units that have to be used to build the circuit, and the results look promising. In FPGAs, the optimizations were not significant and we have identified that some improvement on certain aspects. On the other hand, the results for QCAs are more expressive, reaching optimization rates of 5,54% when compared to QCA standard cells mapping methods, and rates of 11,38% when compared to other techniques.