Simplificações algorítmicas e desenvolvimento de hardware para o In-loop filter do padrão HEVC

Abstract

The filtering process has been an important tool to the video coding since it intends to reduce visual artifacts introduced by the other codification steps, increasing the perceptual quality of the encoded videos. The High Efficiency Video Coding (HEVC) brought a proposal of two new filters inside the In-loop Filter, the Adaptive Loop Filter (ALF) and Sample Adaptive Offset (SAO) which are the focus of this work. Only the SAO filter was inserted in the final standard version but intending to better explore the ALF features it was also included in the investigation presented in this work. This text initially brought a theoretical discussion about these filters and after that we analyzed the filters algorithms in order to simplify them focusing on hardware implementations. The ALF filter involves a series of mathematical calculations on floating point data, which is a critical point for hardware implementations. Therefore, the proposed simplification was to replace these data with integer data. The results of the experiments showed that the impact of this simplification represents an increase of only 0.05% in the bitrate to maintain the same quality when compared to the original ALF execution. However, the simplified algorithm achieves a reduction of 3.38% in the bitrate when compared to a video encoding with the ALF filter disabled. This work also proposed architectures to the ALF cores considering the versions 3 and 5 of the HEVC Test Model (HM) software, and also a configurable version considering the version 3 of HM. In this last case, the architecture uses the same structure to process any of the three filter shapes. The architectures were synthesized to Altera FPGAs and the results shown that the hardwares achieved, at least, a processing rate of 30 UHD 4K frames per second. The SAO filter algorithm was also simplified using integer and fixed point data instead of floating point data. Another simplification proposed was the elimination of full multipliers and dividers applying a loop unrolling technique to the SAO internal cost function and converting these operations in shift-adds. The results showed that the use of the simplifications using integer data caused a bitrate increase of 0.05%. The results also showed a bitrate reduction of 0.0005% when using fixed point data with an 8-bit precision. Based on these simplifications, we proposed an architecture for the SAO internal cost function, which reached a processing rate of 1,634 UHD frames per second. It was also proposed an architecture to perform the classification and statistical collection, in order to allow the offsets generation. This architecture was developed to consume only one sample per cycle and it reached a processing rate of 45UHD 4K frames per second.