Geração automática de redes de transistores dedicada a dispositivos FinFET com gates independentes baseada em composição funcional.

Abstract

The FinFET technology is widely recognized as the leading alternative to solve problems minimization of short-channel effects. This technology consists in the construction of a transistor in three dimensions. Thus, the channel of the FinFET transistor is rounded by the gate in such a way that there is a contact of three faces of the channel with three sides of the gate. The standard structure of a FinFET transistor is known as single-gate (SG) FinFET. However, some variations of this structure have been proposed. One of these structural changes is known as Independent-Gate (IG) FinFET, where a transistor (IG) FinFET can be implemented with two gates. This way, explore the potential provided by (IG) FinFET transistors becomes a powerful strategy to decrease the transistor count in logic gates. This way, explore the potential provided by (IG) FinFET transistors becomes a powerful strategy to decrease the transistor count in logic gates. The method is based on a methodology developed specifically for logic synthesis, known as Functional Composition. It methodology allows controlling the number of associated transistors in parallel or in series. Thus, it simplifies the search for patterns of promising arrangements to explore the potential of devices (IG) FinFET double gate. The experiments have demonstrated that the proposed method is able to generate optimized IG FinFET transistor networks, when compared to methods dedicated to this same purpose.