Desenvolvimento de uma arquitetura para estimação de movimento fracionária segundo o padrão emergente HEVC.

Abstract

The real time processing of high-resolution digital videos is associated with a high computational complexity, mainly due to the necessity of using data compression techniques. Because of this, the development of specific integrated circuits for video processing is an important area of research in digital systems, since software solutions do not allow the required performance for several applications, especially mobile devices. The video encoders have several distinct stages, as transforms, quantization, entropy coding and motion estimation (ME), among others. The step of ME is the most important for the reduction of information to be transmitted, and can use a refinement technique called fractional motion estimation (FME), which helps to improve the results. Many articles can be found in the scientific literature proposing FME architectures for the H.264/AVC (Advanced Video Coding) standard. However, there are few works with FME for the High Efficiency Video Coding (HEVC) standard, which is under development and will be the successor to the H.264/AVC standard. Therefore, the development of efficient architectures for FME according to the HEVC standard is necessary. This work presents the algorithmic study and development of hardware implementations developed for the FME defined in the HEVC standard. The synthesis results show that the developed hardware is able to process Full HD (1920x1080 pixels) and QFHD (3840x2160 pixels) videos in real time.