A Fast Approximate Function Generation Technique to ATMR Design

Abstract

Technological advances provide the production of transistors on a nanometric scale, allowing the production of circuits with a higher transistor density and an increase in the circuit’s operating frequency. However, this transistor miniaturization makes circuits more susceptible to faults. Single events transient can be generated by the collision of energetic particles (such as alpha particles, neutrons, or other heavy ions) with a node in the circuit. These transient events can cause a fault that becomes an error when propagated to a memory element or output. Triple Modular Redundancy is used to mask these faults by generating two copies of the original circuit and connecting the three modules with a majority voter. This strategy can mask 100% of faults that occur in one module. However, it has a high area cost, presenting more than 200% area increase with the modules and the majority voter. Approximate computing concept is used to create modules for the Triple Modular Redundancy architecture to mitigate this area increase. However, the area cost reduction happens in exchange for increasing the fault coverage rate. Therefore, optimizing the tradeoff between area increase and the fault coverage rate is important and challenging. Another critical metric to be optimized is the computational cost to generate these modules, although many methods proposed in the literature do not focus on this metric. The proposed method aims to optimize the computational cost while maintaining a good tradeoff between area increase and fault coverage. The method analyzes the correlation of each input variable with the output, using the variables that have the highest correlation with the output to approximate the modules. The area of the mapped circuit and the error rate of the circuit created using the approximate modules are extracted. The generated circuits have an area increase down to 86.02% and an error rate down to 3.61%. The generation of these functions has a low computational cost, with the largest circuits being approximated in 214 ms. The area and error rate values are worse than those obtained by other methods, but some of these methods take several hours to approximate the same functions used in our analysis.