SINNA: estudo de uma metodologia para aplicação de dimensionamento de transistores em redes não-série-paralelo

Abstract

The microelectronics field has been in increasing development since the last decades, allowing the project flow to be as optimized as possible to meet the requirements demanded by the consumer market. In this sense, the rapid evolution of transistors has made possible the development of circuits on a large scale of integration, thus increasing the complexity of integrated circuit designs. This complexity is related to the minimization of several cost functions, such as area reduction, power and delay. The objective of this work is to investigate the result of the circuit sizing step, when non-series-parallel transistor (NSP) arrangements are part of the circuits tested. Currently, the sizing methods do not perform this type of analysis, and this is one of the motivations for this work, because networks with NSPtype arrangements have a behavior different from the traditional approach (networks consisting only of series-parallel arrays), which may result in oversizing or undersizing of the data resulting from the circuit sizing step. Thus, an approach was developed, called SINNA, which investigates and makes comparisons in circuits composed of NSP transistors. The results showed that networks composed of NSPtype transistor arrangements can affect the quality of the final design if sizing step is performed by traditional sizing approach.