Potencial de reuso de traços em Arquiteturas ARM.

Abstract

The continuous increase in the need for high processing power makes computer designs increasingly complex. Since most of the applications are general purpose, the development of dedicated hardware is often unfeasible. In parallel with the increase in computing power, energy consumption may also be increased. Thus, techniques were developed in order to provide high processing power while reducing or mantaining energy consumption. One of these strategies is called Value Reuse, which exploits recurring and predictable parts that make up most of the executed instructions. The goal of these techniques is to avoid the re-execution of known instructions, which reduces the number of executed instructions and preserves the original context of the application. Value reuse techniques memorize previous executions of instructions, blocks, or traces, with the hope of reusing them when they arise with the same input context again. Although showing great potential for both performance and energy consumption improvement, trace reuse techniques have not been studied for one of the most widely available computer architectures yet: the ARM architecture. ARM processors are common in mobile devices such as cell phones, smartphones, tablets and calculators. This category of devices increasingly demands for processing power, while always committed to a low power consumption. In this work, the architectural features of ARM and its instruction set are evaluated. Afterwards, the potential of reuse of the MiBench benchmarks is analyzed. For this, a trace reuse strategy and its storage structure are presented, which are evaluated with different ways of structuring traces and their impacts in buffers of different sizes. The experiments with MiBench benchmarks show that it is possible to achieve 18.4% of reuse on average using a trace buffer of 32 KiB.